Quickest paths: faster algorithms and dynamization

Given a network $N=(V,E,{c},{l})$, where $G=(V,E)$, $|V|=n$ and $|E|=m$, is a directed graph, ${c}(e) > 0$ is the capacity and ${l}(e) \ge 0$ is the lead time (or delay) for each edge $e\in E$, the quickest path problem is to find a path for a given source--destination pair such that the total lead time plus the inverse of the minimum edge capacity of the path is minimal. The problem has applications to fast data transmissions in communication networks. The best previous algorithm for the single pair quickest path problem runs in time $O(r m+r n \log n)$, where $r$ is the number of distinct capacities of $N$. In this paper, we present algorithms for general, sparse and planar networks that have significantly lower running times. For general networks, we show that the time complexity can be reduced to $O(r^{\ast} m+r^{\ast} n \log n)$, where $r^{\ast}$ is at most the number of capacities greater than the capacity of the shortest (with respect to lead time) path in $N$. For sparse networks, we present an algorithm with time complexity $O(n \log n + r^{\ast} n + r^{\ast} \tilde{\gamma} \log \tilde{\gamma})$, where $\tilde{\gamma}$ is a topological measure of $N$. Since for sparse networks $\tilde{\gamma}$ ranges from $1$ up to $\Theta(n)$, this constitutes an improvement over the previously known bound of $O(r n \log n)$ in all cases that $\tilde{\gamma}=o(n)$. For planar networks, the complexity becomes $O(n \log n + n\log^3 \tilde{\gamma}+ r^{\ast} \tilde{\gamma})$. Similar improvements are obtained for the all--pairs quickest path problem. We also give the first algorithm for solving the dynamic quickest path problem

Quickest Paths: Parallelization And Dynamization

Let N=(V,E,c,l) be a network, where G=(V,E) is a directed graph (|V|=n and |E|=m), c(e)\u3e0 is the capacity and l(e)≥0 is the lead time for each edge e∈E. The transmission time to send σ units of data from a given source s to a destination t using path p is T(σ,p) = l(p) + σ/c(p), where l(p) is the sum of the lead times of the edges in p, and c(p) is the minimum capacity of the edges in p. The quickest path problem is to find a path of minimum transmission time to transmit the σ units of data from s to t. The problem has applications to fast data transmissions in communication networks. We present parallel algorithms for solving the quickest path problem in the case where the network is sparse [i.e. m=O(n)]. We also give algorithms for solving the dynamic quickest path problem. In this problem, the network, the lead times and the capacities on its edges, as well as the amount of data to be transmitted, change over time. The goal is to build a data structure so that one can very quickly compute the quickest path to transmit a given amount of data from any node s to any node t and also, after a dynamic change (edge lead time or edge capacity modification, or edge deletion) on the input network, to be able to update the data structure in an appropriately short time. Furthermore, we improve upon the best sequential result for the single pair quickest path problem which needs O(rm+rn log n) time, where r is the number of distinct edge capacities

A reconfigurable coarse-grain data-path for accelerating computational intensive kernels

In this paper, a high-performance reconfigurable coarse-grain data-path, part of a hybrid reconfigurable platform, is introduced. The data-path consists of coarse-grain components that their flexibility and universality is shown to increase the system’s performance due to significant reductions in latency. A methodology of unsophisticated but efficient algorithms for mapping computational intensive applications on the proposed data-path is also presented. Results on Digital Signal Processing and multimedia benchmarks show an average execution cycles reduction of 20%, combined with an area consumption decrease, when the proposed data-path is compared with a highperformance one. The average cycles reduction is even greater, 44%, when the comparison is held with a data-path that instantiates primitive computational resources on FPGA hardware